This invention relates generally to integrated circuit processing, and more particularly to a method of fabricating a dynamic random access memory with increased capacitance.
One of the goals in the design of dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) is to increase the memory capacity on each integrated circuit. To increase the memory capacity, significant efforts have been made at decreasing the size of each of the memory cells that make up the DRAM. One of the most challenging problems faced by DRAM designers is the maintenance of sufficient charge-storage capacity in the capacitors of the memory cells as their area is decreased, particularly as the area is decreased to sub-micron dimensions.
To maintain sufficient charge-storage capacity in stack capacitor type DRAMs, various techniques have been proposed to increase the effective storage-node area beyond the amount allocated within each memory cell. One such technique involves forming a micro-villus pattern on the storage electrode so as to increase its area. With memory cell areas presently used for DRAM cells, the features of the pattern should not exceed approximately 500 xc3x85. Although features with such dimensions can be made with electron-beam lithography techniques, these techniques are too slow for production quantities, and production quantity lithographic tools cannot create such small features.
Ahn et al., in a paper entitled xe2x80x9cMicro Villus Patterning (MVP) Technology for 256M6 DRAM Stack Cell,xe2x80x9d Symposium on VLSI Technology Digest of Technical Papers, 1992, p. 12, proposed using a thin layer of hemispherical grain (xe2x80x9cHSGxe2x80x9d) polysilicon (also referred to as rough or rugged polysilicon) as an archipelago mask pattern for creating a micro-villus pattern. The HSG polysilicon was deposited on a thin CVD oxide layer. An oxide etch, followed by a polysilicon etch was used to produce the micro-villus pattern. However, HSG grain size and grain spacing are extremely difficult to control, and thus the micro-villus pattern formed with this technique is not evenly spaced, and thus is not optimized for maximum area.
Mine et al., in a paper entitled xe2x80x9cCapacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs,xe2x80x9d Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, p. 137, reported the use of small particles as, an etch mask to form a rough pattern on the lower electrode of a stack capacitor. The Mine et al. approach involves mixing small particles of resist in spin-on glass (xe2x80x9cSOGxe2x80x9d). The mixture is coated on the bottom electrode of a stack DRAM, and the SOG is then selectively etched to leave only the resist particles as a mask on the polysilicon. With this approach, particle size distribution cannot be uniformly controlled, and thus the features of the micro-villus pattern are not optimized. Furthermore, the size of the resist particles is relatively large, on the order of 3,500 xc3x85 in diameter, and thus the features of the lower electrode are relatively large, preventing significant increases in lower electrode area.
Therefore, a need has arisen for a method of fabrication a stack capacitor type DRAM in which a micro-villus pattern is formed on the lower electrode in such a way as to provide significant increases in the area of this electrode. In accordance with the teachings of the present invention, a method of fabricating a micro-villus dynamic random access memory cell is provided which substantially eliminates or reduces disadvantages and problems associated with prior art DRAM memory cells.
In particular, a method of forming a dynamic random access memory cell having a storage capacitor is provided in which a plurality of particles are precipitated in a microemulsion mixture. A lower electrode layer is formed, and the particles are deposited on the lower electrode layer. Using the deposited particles as a mask, a micro-villus pattern is formed on the lower electrode. A dielectric and upper electrode are then formed overlying the lower electrode. In a particular embodiment, the particles are quartz, and are deposited substantially with the Langmuir-Blodgett filming technique.
In another embodiment, a layer of rough polysilicon is formed on the micro-villus pattern so as to further increase the area of the lower electrode.
An important technical advantage of the present invention is the fact that the area of the lower electrode of a stack capacitor type DRAM cell is significantly increased by forming a uniformly distributed micro-villus pattern on the lower electrode. The uniformity of the micro-villus pattern is made possible because a mask is formed with particles prepared through a microemulsion technique. These particles are ultra-fine in size, and can be uniformly distributed, therefore allowing for the evenly distributed micro-villus pattern.